Modélisation au niveau RTL des attaques laser pour l'évaluation des circuits intégrés sécurisés et la conception de contremesures

Many aspects of our current life rely on the exchange of data through electronic media. Powerful encryption algorithms guarantee the security, privacy and authentication of these exchanges. Nevertheless, those algorithms are implemented in electronic devices that may be the target of attacks despite their proven robustness. Several means of attacking integrated circuits are reported in the literature (for instance analysis of the correlation between the processed data and power consumption). Among them, laser illumination of the device has been reported to be one important and effective mean to perform attacks. The principle is to illuminate the circuit by mean of a laser and then to induce an erroneous behavior.For instance, in so-called Differential Fault Analysis (DFA), an attacker can deduce the secret key used in the crypto-algorithms by comparing the faulty result and the correct one. Other types of attacks exist, also based on fault injection but not requiring a differential analysis; the safe error attacks or clocks attacks are such examples.The main goal of the PhD thesis was to provide efficient CAD tools to secure circuit designers in order to evaluate counter-measures against such laser attacks early in the design process. This thesis has been driven by two Grenoble INP laboratories: LCIS and TIMA. The work has been carried out in the frame of the collaborative ANR project LIESSE involving several other partners, including STMicroelectronics.A RT level model of laser effects has been developed, capable of emulating laser attacks. The fault model was used in order to evaluate several different secure cryptographic implementations through FPGA emulated fault injection campaigns. The injection campaigns were performed in collaboration with TIMA laboratory and they allowed to compare the results with other state of the art fault models. Furthermore, the approach was validated versus the layout of several circuits. The layout based validation allowed to quantify the effectiveness of the fault model to predict localized faults. Additionally, in collaboration with CMP (Centre Microélectronique de Provence) experimental laser fault injections has been performed on a state of the art STMicroelectronics IC and the results have been used for further validation of the fault model. Finally the validated fault model led to the development of an RTL (Register Transfer Level) countermeasure against laser attacks. The countermeasure was implemented and evaluated by fault injection campaigns according to the developed fault model, other state of the art fault models and versus layout information.De nombreux aspects de notre vie courante reposent sur l'échange de données grâce à des systèmes de communication électroniques. Des algorithmes de chiffrement puissants garantissent alors la sécurité, la confidentialité et l'authentification de ces échanges. Néanmoins, ces algorithmes sont implémentés dans des équipements qui peuvent être la cible d'attaques. Plusieurs attaques visant les circuits intégrés sont rapportées dans la littérature. Parmi celles-ci, les attaques laser ont été rapportées comme étant très efficace. Le principe consiste alors à illuminer le circuit au moyen d'un faisceau laser afin d'induire un comportement erroné et par analyse différentielle (DFA) afin de déduire des informations secrètes.L'objectif principal de cette thèse est de fournir des outils de CAO efficaces permettant de sécuriser les circuits en évaluant les contre-mesures proposées contre les attaques laser et cela très tôt dans le flot de conception.Cette thèse est effectuée dans le cadre d'une collaboration étroite entre deux laboratoires de Grenoble INP : le LCIS et le TIMA. Ce travail est également réalisé dans le cadre du projet ANR LIESSE impliquant plusieurs autres partenaires, dont notamment STMicroelectronics.Un modèle de faute au niveau RTL a été développé afin d’émuler des attaques laser. Ce modèle de faute a été utilisé pour évaluer différentes architectures cryptographiques sécurisées grâce à des campagnes d'injection de faute émulées sur FPGA.Ces campagnes d'injection ont été réalisées en collaboration avec le laboratoire TIMA et elles ont permis de comparer les résultats obtenus avec d'autres modèles de faute. De plus, l'approche a été validée en utilisant une description au niveau layout de plusieurs circuits. Cette validation a permis de quantifier l'efficacité du modèle de faute pour prévoir des fautes localisées. De plus, en collaboration avec le CMP (Centre de Microélectronique de Provence) des injections de faute laser expérimentales ont été réalisées sur des circuits intégrés récents de STMICROELECTRONICS et les résultats ont été utilisés pour valider le modèle de faute RTL.Finalement, ce modèle de faute RTL mène au développement d'une contremesure RTL contre les attaques laser. Cette contre-mesure a été mise en œuvre et évaluée par des campagnes de simulation de fautes avec le modèle de faute RTL et d'autres modèles de faute classiques

Excision Repair Cross-Complementation Group 1 Enzyme as a Molecular Determinant of Responsiveness to Platinum-Based Chemotherapy for non Small-Cell Lung Cancer

Although platinum-based chemotherapy remains the “standard” in advanced non small-cell lung cancer, not all patients derive clinical benefit from such a treatment. Hence, the development of predictive biomarkers able to identify lung cancer patients who are most likely to benefit from cisplatin-based chemotherapy has become a scientific priority. Among the molecular pathways involved in DNA damage control after chemotherapy, the nucleotide excision repair (NER) is a critical process for the repair of DNA damage caused by cisplatin-induced DNA adducts. Many reports have explored the role of the excision repair cross-complementation group 1 enzyme (ERCC1) expression in the repair mechanism of cisplatin-induced DNA adducts in cancer cells

On a Side Channel and Fault Attack Concurrent Countermeasure Methodology for MCU-based Byte-sliced Cipher Implementations

As IoT applications are increasingly being deployed, there comes along an ever increasing need for the security and privacy of the involved data. Since cryptographic implementations are used to achieve these goals, it is important for embedded software developers to take into consideration hardware attacks. Side Channel Analysis (SCA) and Fault Attacks (FA) are the main classes of such attacks, which can either reduce or even eliminate the security levels of an em-bedded design. Therefore, cryptographic implementations must address both of them at the same time. To this end, multiple solutions have been proposed to address both attacks in one solution, such as Dual Pre-charge Logic (DPL) and Encoding countermeasures. In this work, we discuss the advantages and disadvantages of the state of the art, concurrent SCA and FA countermeasures. Additionally, we propose a software countermeasure in order to provide protection against both types of attacks. The proposed countermeasure is a general approach, applicable to any byte-sliced cipher and any modern MCUs (32- and 64-bit). The proposed countermeasure is ap-plied to an AES S-BOX implementation, for a 32-bit MCU (ARM Cortex-M3). The countermeasure has been experimen-tally evaluated against Correlation Power Analysis (CPA) attacks for both platforms while its fault detection capabilities are theoretically described

Quantitative determination of glycosaminoglycans in tears of diabetic patients

Marilita M Moschos1, Alexandros A Rouvas1, Spyridon Papadimitriou1, Athanasios Kotsolis1, Nikolaos Sitaras2, Michael Apostolopoulos11Department of Ophthalmology; 2Department of Pharmacology, University of Athens, GreecePurpose: To determine the amount of glycosaminoglycans (GAGs) in tears of patients with diabetic retinopathy (DR) and to compare it with normal subjects.Methods: 38 patients with DR and 24 normal volunteers were included. Thirty subjects suffered from background diabetic retinopathy (BDR) and 8 from proliferate diabetic retinopathy (PDR). For the GAGs assay, the uronic carbazole reaction was used.Results: The mean concentration of GAGs was significantly higher in patients with DR than in normal subjects. The GAGs concentration in patients with BDR or PDR was significantly higher than in normal subjects.Conclusion: The measurement of GAGs in tears of diabetic patients could be a tool in order to assess the stability or not of the disease.Keywords: glycosaminoglycans, tears, diabetic retinopath

Review and ranking of crash risk factors related to the road infrastructure

The objective of this paper is the review and comparative assessment of infrastructure related crash risk factors, with the explicit purpose of ranking them based on how detrimental they are towards road safety (i.e. crash risk, frequency and severity). This analysis was carried out within the SafetyCube project, which aimed to identify and quantify the effects of risk factors and measures related to behaviour, infrastructure or vehicles, and integrate the results in an innovative road safety Decision Support System (DSS). The evaluation was conducted by examining studies from the existing literature. These were selected and analysed using a specifically designed common methodology. Infrastructure risk factors were structured in a hierarchical taxonomy of 10 areas with several risk factors in each area (59 specific risk factors in total), examples include: alignment features (e.g. horizontal-vertical alignment deficiencies), cross-section characteristics (e.g. superelevation, lanes, median and shoulder deficiencies), road surface deficiencies, workzones, junction deficiencies (interchange and at-grade) etc. Consultation with infrastructure stakeholders (international organisations, road authorities, etc.) took place in dedicated workshops to identify user needs for the DSS, as well as “hot topics” of particular importance. The following analysis methodology was applied to each infrastructure risk factor: (i) A search for relevant international literature, (ii) Selection of studies on the basis of rigorous criteria, (iii) Analysis of studies in terms of design, methods and limitations, (iv) Synthesis of findings - and meta-analysis, when feasible. In total 243 recent and high quality studies were selected and analysed. Synthesis of results was made through 39 ‘Synopses’ (including 4 original meta-analyses) on individual risk factors or groups of risk factors. This allowed the ranking of infrastructure risk factors into three groups: risky (11 risk factors), probably risky (18 risk factors), and unclear (7 risk factors)

Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins

Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core GPUs, and programmable FPGAs. The effective utilization of these architectures poses several challenges, among which a primary one is power consumption. Voltage reduction is one of the most efficient methods to reduce power consumption of a chip. With the galloping adoption of hardware accelerators (i.e., GPUs and FPGAs) in large datacenters and other large-scale computing infrastructures, a comprehensive evaluation of the safe voltage reduction levels for each different chip can be employed for efficient reduction of the total power. We present a survey of recent studies in voltage margins reduction at the system level for modern CPUs, GPUs and FPGAs. The pessimistic voltage guardbands inserted by the silicon vendors can be exploited in all devices for significant power savings. On average, voltage reduction can reach 12% in multicore CPUs, 20% in manycore GPUs and 39% in FPGAs.Comment: Accepted for publication in IEEE Transactions on Device and Materials Reliabilit